module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);

    localparam FSM_W  = 3;
    localparam FSM_W1 = FSM_W - 1'b1;

    reg [FSM_W1:0]   state;
    reg [FSM_W1:0]   nxt_state;

    localparam  IDLE        = 0;
    localparam  S_1         = 1;
    localparam  S_0         = 2;

    reg [1:0]       asrt_cntr;
    wire            asrt_cntr_add;  
    wire            asrt_cntr_clr;  

    //assert signal cntr
    always @(posedge clk) begin
        if(reset) begin
            asrt_cntr              <= 'b0;
        end else if(asrt_cntr_add)begin
            asrt_cntr              <= asrt_cntr + 1'b1;
        end else if(asrt_cntr_clr)begin
            asrt_cntr              <= 'b0;
        end
    end
    assign                  asrt_cntr_add  = state[S_1   ];
    assign                  asrt_cntr_clr  = 1'b0; // cntr clear itself


    // State transition logic (combinational)
    always @(*) begin
        nxt_state[IDLE   ]          =   1'b0; // never reach for nxt_state
        nxt_state[S_1    ]          =   state[IDLE   ] || (state[S_1] && ~(asrt_cntr == 2'd3));
        nxt_state[S_0    ]          =   (state[S_1] && asrt_cntr == 2'd3) || state[S_0   ];
    end

    // State flip-flops (sequential)
    always @(posedge clk) begin
        if(reset)
            state   <=  'b1; //IDLE
        else begin
            state   <=  nxt_state;
        end  
    end

    //output logic
    assign  shift_ena    =   nxt_state[S_1];

endmodule
